EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
ICCD
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper presents a new approach to the automated generation of an initialization sequence for synchronous sequential circuits. Finding an initialization sequence is a hard task...
ATS
1997
IEEE
13 years 9 months ago
1997
IEEE
Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate in...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on th...