ISSS
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
FPL
2003
Springer
13 years 9 months ago
2003
Springer
At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map fast and efficiently applications written in Matlab onto recon...