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DDECS
2007
IEEE
90views Hardware» more  DDECS 2007»
9 years 5 months ago
Test Pattern Generator for Delay Faults
A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this r...
Tomasz Rudnicki, Andrzej Hlawiczka
IOLTS
2000
IEEE
105views Hardware» more  IOLTS 2000»
9 years 5 months ago
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
Patrick Girard, Christian Landrault, Serge Pravoss...
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