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DELTA
2004
IEEE
10 years 2 months ago
Scan Test of IP Cores in an ATE Environment
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi
ETS
2006
IEEE
93views Hardware» more  ETS 2006»
10 years 4 months ago
Retention-Aware Test Scheduling for BISTed Embedded SRAMs
In this paper we address the test scheduling problem for Builtin Self-tested (BISTed) embedded SRAMs (e-SRAMs) when Data Retention Faults (DRFs) are considered. The proposed test ...
Qiang Xu, Baosheng Wang, F. Y. Young
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