Retention-Aware Test Scheduling for BISTed Embedded SRAMs

In this paper we address the test scheduling problem for Builtin Self-tested (BISTed) embedded SRAMs (e-SRAMs) when Data Retention Faults (DRFs) are considered. The proposed test scheduling algorithm utilizes the ”retention-aware” test power model [1] to minimize the total testing time of eSRAMs while not violating given power constraints. Without losing generality, we consider both cases where the pause time for data retention faults is fixed and cases where it can be varied. Experimental results show that the ”retention-aware” test scheduling algorithm can reduce the testing time of eSRAMs up to more than 98 percent at the computational time within a second.

• Type: Conference
• Year: 2006
• Where: ETS
• Authors: Qiang Xu, Baosheng Wang, F. Y. Young
• Keywords: Data Retention Faults, ETS 2006, Hardware, Test Scheduling, Test Scheduling Algorithm