Sciweavers

VLSID
2005
IEEE
89views VLSI» more  VLSID 2005»
14 years 5 months ago
Power Optimization in Current Mode Circuits
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
M. S. Bhat, H. S. Jamadagni