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    GLVLSI
    2005
    IEEE
    199views VLSI» more  GLVLSI 2005»
    Interconnect delay minimization through interlayer via placement in 3-D ICs
    13 years 10 months ago
    Interconnect delay minimization through interlayer via placement in 3-D ICs
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    The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
    Vasilis F. Pavlidis, Eby G. Friedman
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