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VLSID
1997
IEEE
173views VLSI» more  VLSID 1997»
13 years 8 months ago
Formal Verification of Digital Systems
Gitanjali Swamy
VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
13 years 8 months ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick
VLSID
1997
IEEE
106views VLSI» more  VLSID 1997»
13 years 8 months ago
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
I n this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power archite...
S. Ramanathan, V. Visvanathan
VLSID
1997
IEEE
91views VLSI» more  VLSID 1997»
13 years 8 months ago
Behavioral Array Mapping into Multiport Memories Targeting Low Power
Preeti Ranjan Panda, Nikil D. Dutt
VLSID
1997
IEEE
102views VLSI» more  VLSID 1997»
13 years 8 months ago
Optimal Clock Period for Synthesized Data Paths
A. R. Naseer, M. Balakrishnan, Anshul Kumar
VLSID
1997
IEEE
399views VLSI» more  VLSID 1997»
13 years 8 months ago
A Self-Biased High Performance Folded Cascode CMOS Op-Amp
Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise...
Pradip Mandal, V. Visvanathan
VLSID
1997
IEEE
135views VLSI» more  VLSID 1997»
13 years 8 months ago
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxen...
VLSID
1997
IEEE
116views VLSI» more  VLSID 1997»
13 years 8 months ago
Allocation of FIFO Structures in RTL Data Paths
Heman Khanna, M. Balakrishnan
VLSID
1997
IEEE
112views VLSI» more  VLSID 1997»
13 years 8 months ago
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs
An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA ...
James Jacob, P. Srinivas Sivakumar, Vishwani D. Ag...