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VLSID
2000
IEEE
75views VLSI» more  VLSID 2000»
13 years 9 months ago
Timing Analysis with Implicitly Specified False Paths
We consider the problem of timing analysis in the presence of known false paths. The main difficulty in adaptation of classical breadth-first search to the problem is that at each...
Eugene Goldberg, Alexander Saldanha
VLSID
2000
IEEE
164views VLSI» more  VLSID 2000»
13 years 9 months ago
A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation
Digital images are convenient media for describing and storing spatial, temporal, spectral, and physical components of information contained in a variety of domains(e.g. aerial/sa...
Sabyasachi Dey, Bhargab B. Bhattacharya, Malay Kum...
VLSID
2000
IEEE
89views VLSI» more  VLSID 2000»
13 years 9 months ago
Specification and Design of a Quasi-Delay-Insensitive Java Card
Fu-Chiung Cheng, Chuin-Ren Wang
VLSID
2000
IEEE
95views VLSI» more  VLSID 2000»
13 years 9 months ago
Hierarchical Error Diagnosis Targeting RTL Circuits
Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to lo...
Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee...