VTS
1998
IEEE
13 years 9 months ago
1998
IEEE
A fast fault-tolerant controller structure is presented, which is capable of recovering from transient faults by performing a rollback operation in hardware. The proposed fault-to...
VTS
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
VTS
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
VTS
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators TPGs. Bit transition maximiz...
VTS
1998
IEEE
13 years 9 months ago
1998
IEEE
An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed ...