A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding

We propose a high-performance hardware accelerator for intra prediction and mode decision in H.264/AVC video encoding. We use two intra prediction units to increase the performance. Taking advantage of function similarity and data reuse, we successfully reduce the hardware cost of the intra prediction units. Based on a modified mode decision algorithm, our design can deliver almost the same video quality as the reference software. We have implemented the proposed architecture in Verilog and synthesized it targeting towards a TSMC 0.13pm CMOS cell library. Running at 75MHz, our 36K-gate circuit is capable of realtime encoding 720p HD (1280x720) video sequences at 30 frames per second (fps).

• Type: Conference
• Year: 2006
• Where: APCCAS
• Authors: Yu-Chien Kao, Huang-Chih Kuo, Yin-Tzu Lin, Chia-Wen Hou, Yi-Hsien Li, Hao-Tin Huang, Youn-Long Lin
• Keywords: APCCAS 2006, Hardware, Intra Prediction, Intra Prediction Units, Mode Decision