An 830mW, 586kbps 1024-bit RSA chip design

This paper presents an RSA hardware design that simultaneously achieves high-performance and lowpower. A bit-oriented, split modular multiplication algorithm and architecture are proposed to fully exert the radix-4 computational capability. Further, we identify the switching profile of RSA data and accordingly propose power-optimized designs for the storage elements and key computational components. The complete RSA modular exponentiation hardware has been implemented using cell-based 0.18um CMOS technology. Post-layout simulation shows that the design delivers an average performance of 586kbps at

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang
• Keywords: DATE 2006, Hardware, RSA Hardware Design, RSA Modular Exponentiation, Split Modular Multiplication