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DATE
2006
IEEE
78views Hardware» more  DATE 2006»
11 years 9 months ago
A time-triggered ethernet (TTE) switch
This paper presents the design of a Time-Triggered Ethernet (TTE) Switch, which is one of the core units of the Time-Triggered Ethernet system. Time-triggered Ethernet is a commun...
Klaus Steinhammer, Petr Grillinger, Astrit Ademaj,...
DATE
2006
IEEE
95views Hardware» more  DATE 2006»
11 years 9 months ago
Satisfiability-based framework for enabling side-channel attacks on cryptographic software
- Many electronic systems contain implementations of cryptographic algorithms in order to provide security. It is well known that cryptographic algorithms, irrespective of their th...
Nachiketh R. Potlapally, Anand Raghunathan, Srivat...
DATE
2006
IEEE
119views Hardware» more  DATE 2006»
11 years 9 months ago
Compiler-driven FPGA-area allocation for reconfigurable computing
In this paper, we propose two FPGA-area allocation algorithms based on profiling results for reducing the impact on performance of dynamic reconfiguration overheads. The problem o...
Elena Moscu Panainte, Koen Bertels, Stamatis Vassi...
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
11 years 9 months ago
Compositional, efficient caches for a chip multi-processor
In current multi-media systems major parts of the functionality consist of software tasks executed on a set of concurrently operating processors. Those tasks interfere with each o...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
11 years 9 months ago
Battery-aware code partitioning for a text to speech system
The advent of multi-core embedded processors has brought along new challenges for embedded system design. This paper presents an efficient, battery aware, code partitioning techni...
Anirban Lahiri, Anupam Basu, Monojit Choudhury, Sr...
DATE
2006
IEEE
97views Hardware» more  DATE 2006»
11 years 9 months ago
Monolithic verification of deep pipelines with collapsed flushing
We introduce collapsed flushing, a new flushing-based refinement map for automatically verifying safety and liveness properties of term-level pipelined machine models. We also pre...
Roma Kane, Panagiotis Manolios, Sudarshan K. Srini...
DATE
2006
IEEE
84views Hardware» more  DATE 2006»
11 years 9 months ago
Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology
Lakshmi N. Chakrapani, Bilge E. S. Akgul, Suresh C...
DATE
2006
IEEE
128views Hardware» more  DATE 2006»
11 years 9 months ago
Platform-based design of wireless sensor networks for industrial applications
We present a methodology, an environment and supporting tools to map an application on a wireless sensor network (WSN). While the method is quite general, we use extensively an exa...
Alvise Bonivento, Luca P. Carloni, Alberto L. Sang...
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
11 years 9 months ago
Efficient incremental clock latency scheduling for large circuits
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
Christoph Albrecht
DATE
2006
IEEE
95views Hardware» more  DATE 2006»
11 years 9 months ago
Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications
Network applications are becoming increasingly popular in the embedded systems domain requiring high performance, which leads to high energy consumption. In networks is observed t...
Alexandros Bartzas, Stylianos Mamagkakis, Georgios...
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