Exploiting processing locality through paging configurations in multitasked reconfigurable systems

FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of hardware functions to be configured typically exceeds the underlying chip area during the execution of an application, previous efforts have introduced configuration caching. Those efforts, however, have focused on two run-time-reconfiguration scenarios, which consider a single application running on the reconfigurable system. In the full reconfiguration scenario, functions of an application are arranged into blocks each of which has enough functions to fill the entire chip. The blocks are configured in a deterministic sequence needed by the application based on the a priori knowledge about the application. In the partial reconfiguration scenario, each function is configured or replaced on a function-by-function basis, based on the application needs. In the former technique, spatial processing locality is wel...

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: T. Taher, Tarek A. El-Ghazawi
• Keywords: Distributed And Parallel Computing, Hardware Functions, IPPS 2006, Processing Locality, Reconfiguration Scenario