Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking

—A low-latency, HDL-synthesizable dynamic clock frequency controller is presented as a time-efficient alternative to full-custom implementations. Frequency division of a fully integrated hybrid temperature-compensated LC oscillator (TC-LCO) and ring oscillator clock reference avoids PLL locking delays to enable low-latency, hazard-free frequency selection on an actively running CPU. Fabricated in 0.18µm CMOS as part of a low-power SoC microsystem, the circuit

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Robert M. Senger, Eric D. Marsman, Gordy A. Carichner, Sundus Kubba, Michael S. McCorquodale, Richard B. Brown
• Keywords: Clock Frequency Controller, ISCAS 2006, Ring Oscillator Clock, —A Low-latency