A reconfigurable design-for-debug infrastructure for SoCs

In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters. Categories and Subject Descriptors B.7 [Integrated circuits]; J.6 [Computer-aided engineering] General Terms Verification, Performance, Design, Economics, Experimentation.

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Miron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi, Dave Miller
• Keywords: Computer Architecture, DAC 2006, Debug Platform, Distributed Reconfigurable Fabric, In-system Functional Debug