FPGA based Agile Algorithm-On-Demand Co-Processor

With growing computational needs of many real-world applications, frequently changing specifications of standards, and the high design and NRE costs of ASICs, an algorithm-agile FPGA based co-processor has become a viable alternative. In this article, we report about the general design of an algorith-agile co-processor and the proof-ofconcept implementation.

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti
• Keywords: Algorith-agile Co-processor, DATE 2005, FPGA Based Co-processor, Hardware, NRE Costs