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11

FPT
2005
IEEE

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Post-Silicon Debug Using Programmable Logic Cores

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Post-Silicon Debug Using Programmable Logic Cores

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Producing a functionally correct integrated circuit is becoming increasingly difficult. No matter how careful a designer is, there will always be integrated circuits that are fabricated, but do not operate as expected. Providing a means to effectively debug these integrated circuits is vital to help pin-point problems and reduce the number of re-spins required to create a correctly-functioning chip. In this paper, we show that programmable logic cores (PLCs) and flexible networks can provide this debugging capability. We present an architecture and example implementation. We show that the area overhead of this proposed architecture would be well below 10% for many target ICs.

Bradley R. Quinton, Steven J. E. Wilton

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Correct Integrated Circuit | FPT 2005 | Hardware | Integrated Circuits | Programmable Logic Cores |

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Added	24 Jun 2010
Updated	24 Jun 2010
Type	Conference
Year	2005
Where	FPT
Authors	Bradley R. Quinton, Steven J. E. Wilton

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