Cooperative Instruction Scheduling with Linear Scan Register Allocation

Abstract. Linear scan register allocation is an attractive register allocation algorithm because of its simplicity and fast running time. However, it is generally felt that linear scan register allocation yields poorer code than allocation schemes based on graph coloring. In this paper, we propose a pre-pass instruction scheduling algorithm that improves on the code quality of linear scan allocators. Our implementation in the Trimaran compiler-simulator infrastructure shows that our scheduler can reduce the number of active live ranges that the linear scan allocator has to deal with. As a result, fewer spills are needed and the quality of the generated code is improved. Furthermore, compared to the default scheduling and graph coloring allocator schemes found in the IMPACT and Elcor components of Trimaran, our implementation with our prepass scheduler and linear scan register allocator significantly reduced compilation times.

• Type: Conference
• Year: 2005
• Where: HIPC
• Authors: Khaing Khaing Kyi Win, Weng-Fai Wong
• Keywords: HIPC 2005, Linear Scan, Linear Scan Register, Scan Register Allocation