A Parallel State Assignment Algorithm for Finite State Machines

This paper summarizes the design and implementation of a parallel algorithm for state assignment of large Finite State Machines (FSMs). High performance CAD tools are necessary to overcome the computational complexity involved in the optimization of large sequential circuits. FSMs constitute an important class of logic circuits, and state assignment is one of the key steps in combinational logic optimization. The SMPbased parallel algorithm — based on the sequential program JEDI targeting multilevel logic implementation — scales nearly linearly with the number of processors for FSMs of varying problem sizes chosen from standard benchmark suites while attaining quality of results comparable to the best sequential algorithms. ∗ This work was supported in part by NSF Grants CAREER ACI-00-93039, ITR ACI-00-81404, DEB-9910123, ITR EIA-01-21377, Biocomplexity DEB-01-20709, and ITR EF/BIO 03-31654. † Supported in part by an NSF Research Experience for Undergraduates (REU) grant. 1 

• Type: Conference
• Year: 2004
• Where: HIPC
• Authors: David A. Bader, Kamesh Madduri
• Keywords: HIPC 2004, Large Sequential Circuits, Parallel Algorithm, State Assignment