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DAC
1996
ACM

A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines

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A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines
Abstract-- This paper proposes a state reduction algorithm for incompletely specified FSMs. The algorithm is based on iterative improvements. When the number of compatibles is likely to be too large to handle explicitly, they are represented by a BDD. Experimental results are given to demonstrate that the algorithm described here is faster and obtains better solutions than conventional methods.
Hiroyuki Higuchi, Yusuke Matsunaga
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1996
Where DAC
Authors Hiroyuki Higuchi, Yusuke Matsunaga
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