A Proposal for Transaction-Level Verification with Component Wrapper Language

We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, and simulation-coverage analyzer. This approach combines the conventional transaction level language such as C and the signal level language based on our previously developed Component Wrapper Language (CWL). This approach is based on two concepts. The first one is a complete separation between transaction-level verification and signal-level verification for generating suitable verification suites in each design phase. The second one is the quick generation of signal-level verification suites from the original specification written in CWL. Experimental results show that our approach should yield much shorter verification periods versus conventional methods.

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Koji Ara, Kei Suzuki
• Keywords: DATE 2003, Hardware, Signal-level Verification, Transaction Level Verification, Verification Suites