Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation

Abstract— This paper proposes to speedup sampled microprocessor simulations by reducing warmup times without sacrificing simulation accuracy. It exploiting the observation that of the memory references that precede a sample cluster, references that occur nearest to the cluster are more likely to be germane to the execution of the cluster itself. Hence, while modeling all cache and branch predictor interactions that precede a sample cluster would reliably establish their state, this is overkill and leads to longrunning simulations. Instead, accurately establishing simulated cache and branch predictor state can be accomplished quickly by only modeling a subset of the memory references and controlflow instructions immediately preceding a sample cluster. Our technique measures memory reference reuse latencies (MRRLs)—the number of completed instructions between consecutive references to each unique memory location—and uses these data to choose a point prior to each cluster to engag...

• Type: Conference
• Year: 2003
• Where: ISPASS
• Authors: John W. Haskins Jr., Kevin Skadron
• Keywords: Branch Predictor, Branch Predictor Interactions, ISPASS 2003, Sample Cluster, Software Engineering