Sciweavers

MAM
2002
63views more  MAM 2002»
13 years 4 months ago
OPTS: increasing branch prediction accuracy under context switch
Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors. Though many dynamic branch predictors have been proposed to obtain high...
Moon-Sang Lee, Young-Jae Kang, Joonwon Lee, Seung ...
CAL
2007
13 years 4 months ago
Branch Misprediction Prediction: Complementary Branch Predictors
1 – In this paper, we propose a new class of branch predictors, complementary branch predictors, which can be easily added to any branch predictor to improve the overall predicti...
Resit Sendag, Joshua J. Yi, Peng-fei Chuang
ASPLOS
2008
ACM
13 years 7 months ago
Accurate branch prediction for short threads
Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to e...
Bumyong Choi, Leo Porter, Dean M. Tullsen
EXPCS
2007
13 years 8 months ago
Introducing entropies for representing program behavior and branch predictor performance
Predictors are inherent components of state-of-the-art microprocessors. Branch predictors are discussed actively from diverse perspectives. Performance of a branch predictor large...
Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba
MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
13 years 9 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin
MICRO
2000
IEEE
84views Hardware» more  MICRO 2000»
13 years 9 months ago
The impact of delay on the design of branch predictors
Modern microprocessors employ increasingly complicated branch predictors to achieve instruction fetch bandwidth that is sufficient for wide out-of-order execution cores. While ex...
Daniel A. Jiménez, Stephen W. Keckler, Calv...
ISHPC
2003
Springer
13 years 10 months ago
Tolerating Branch Predictor Latency on SMT
Abstract. Simultaneous Multithreading (SMT) tolerates latency by executing instructions from multiple threads. If a thread is stalled, resources can be used by other threads. Howev...
Ayose Falcón, Oliverio J. Santana, Alex Ram...
ISPASS
2003
IEEE
13 years 10 months ago
Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation
Abstract— This paper proposes to speedup sampled microprocessor simulations by reducing warmup times without sacrificing simulation accuracy. It exploiting the observation that ...
John W. Haskins Jr., Kevin Skadron
ISCA
2005
IEEE
113views Hardware» more  ISCA 2005»
13 years 10 months ago
Piecewise Linear Branch Prediction
Improved branch prediction accuracy is essential to sustaining instruction throughput with today’s deep pipelines. We introduce piecewise linear branch prediction, an idealized ...
Daniel A. Jiménez
IEEEPACT
2005
IEEE
13 years 10 months ago
A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction
The continual demand for greater performance and growing concerns about the power consumption in highperformance microprocessors make the branch predictor a critical component of ...
Gabriel H. Loh