Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address

Phase change memory (PCM) is an emerging memory technology for future computing systems. Compared to other non-volatile memory alternatives, PCM is more matured to production, and has a faster read latency and potentially higher storage density. The main roadblock precluding PCM from being used, in particular, in the main memory hierarchy, is its limited write endurance. To address this issue, recent studies proposed to either reduce PCM’s write frequency or use wear-leveling to evenly distribute writes. Although these techniques can extend the lifetime of PCM, most of them will not prevent deliberately designed malicious codes from wearing it out quickly. Furthermore, all the prior techniques did not consider the circumstances of a compromised OS and its security implication to the overall PCM design. A compromised OS will allow adversaries to manipulate processes and exploit side channels to accelerate wear-out. In this paper, we argue that a PCM design not only has to consider no...

• Type: Conference
• Year: 2010
• Where: ISCA
• Authors: Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee
• Keywords: Hardware, ISCA 2010, PCM Design, PCM’s Write Frequency, Roadblock Precluding Pcm