Performance of On-Chip Multiprocessors for Vision Tasks

Abstract. Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available on a single chip, the “on-chip multiprocessor” has been proposed as a promising alternative to processors based on the superscalar architecture. This paper examines the performance of vision benchmark tasks on an on-chip multiprocessor. To evaluate the performance, a program-driven simulator and its programming environment were developed. DARPA IU benchmarks were used for evaluation purposes. The benchmark includes integer, floating point, and extensive data movement operations. The simulation results show that the proposed on-chip multiprocessor can exploit thread-level parallelism effectively.

• Type: Conference
• Year: 2000
• Where: IPPS
• Authors: Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Viktor K. Prasanna
• Keywords: Distributed And Parallel Computing, IPPS 2000, On-chip Multiprocessor, Superscalar Architecture, Vision Benchmark Tasks