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15

ASPDAC
2000
ACM

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A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL

13 years 9 months ago

A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL

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Hirofumi Sakamoto, Ken'ichiro Uda, Bu-Y. Lee, Hiro

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ASPDAC 2000 | Hardware |

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Added	01 Aug 2010
Updated	01 Aug 2010
Type	Conference
Year	2000
Where	ASPDAC
Authors	Hirofumi Sakamoto, Ken'ichiro Uda, Bu-Y. Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda

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