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8

ASPDAC
1999
ACM

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A High Speed and Low Power Phase-Frequency Detector and Charge - pump

13 years 9 months ago

A High Speed and Low Power Phase-Frequency Detector and Charge - pump

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– In this paper, we introduce a high-speed and low power Phase-Frequency Detector (PFD) that is designed using modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop. This PFD has a simpler structure with using only 19 transistors. The operation range of this PFD is

Won Hyo Lee, Jun Dong Cho, Sung Dae Lee

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ASPDAC 1999 | Hardware | Power Phase-frequency Detector | Simpler Structure | True Single-Phase Clock |

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Added	02 Aug 2010
Updated	02 Aug 2010
Type	Conference
Year	1999
Where	ASPDAC
Authors	Won Hyo Lee, Jun Dong Cho, Sung Dae Lee

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