Performance Prediction Tools for Parallel Discrete-Event Simulation

We have developed a set of performance prediction tools which help to estimate the achievable speedups from parallelizing a sequential simulation. The tools focus on two important factors in the actual speedup of a parallel simulation program : (a) the simulation protocol used, and (b) the inherent parallelism in the simulation model. The first two tools are a performance/parallelism analyzer for a conservative, asynchronous simulation protocol, and a similar analyzer for a conservative, synchronous (“super-step”) protocol. Each analyzer allows us to study how the speedup of a model changes with increasing number of processors, when a specific protocol is used. The third tool – a critical path analyzer – gives an ideal upper bound to the model’s speedup. This paper gives an overview of the prediction tools, and reports the predictions from applying the tools to a discrete-event wafer fabrication simulation model. The predictions are close to speedups from actual parallel i...

• Type: Conference
• Year: 1999
• Where: PADS
• Authors: Chu-Cheow Lim, Yoke-Hean Low, Boon-Ping Gan, Sanjay Jain, Wentong Cai, Wen-Jing Hsu, Shell-Ying Huang
• Keywords: Modelling And Simulation, PADS 1999, Parallel Simulation Program, Simulation, Simulation Protocol