Logical Verification of the NVAX CPU Chip Design

ct Digital's NVAX high-performance microprocessor has a complex logical design. A rigorous simulation-based verification effort was undertaken to ensure that there were no logical errors. At the core of the effort were implementation-oriented, directed, pseudorandom exercisers. These exercisers were supplemented with implementation-specific focused tests and existing VAX architectural tests. Only 15 logical bugs, all unobtrusive, were detected in the first-pass design, and the operating system booted with first-pass chips in a prototype system.

• Type: Conference
• Year: 1992
• Where: ICCD
• Authors: Walker Anderson
• Keywords: Complex Logical Design, Hardware, ICCD 1992, Logical Errors, Simulation-based Verification Effort