Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators

Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time algorithm for scheduling reconfiguration tasks given a trace of actors (invocations of hardware kernels) that is both provably optimal and placement-aware. In addition, we will propose a dependence analysis to determine whether for each actor instance, a reconfiguration task is needed prior to its execution in hardware. A case study using the H.264 encoder is presented to compare our algorithm against the state-of-the-art heuristics.

• Type: Conference
• Year: 2009
• Where: FCCM
• Authors: Joon Edward Sim, Weng-Fai Wong, Jürgen Teich
• Keywords: FCCM 2009, Partial Reconfiguration, Polynomial Time Algorithm, Reconfiguration Task, VLSI