Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocesso

Abstract - We propose an integrated archltectural/physicdplanning approach named priority assignment optimization to mioimize the current surge in high performance power eifkient clock-gated microprocessors. The proposed approach balances the current demands across the floorplan by assigning optimized priorities to the functional unlts (FUs). Two complementary methods - physical planning with soft modules and h o e pattern management - to enhance our proposed approach are also dlscussed for various applications. Experimental results show

• Type: Conference
• Year: 2004
• Where: ASPDAC
• Authors: Yiran Chen, Kaushik Roy, Cheng-Kok Koh
• Keywords: Approach Balances, Approach Named Priority, ASPDAC 2004, Eifkient Clock-gated Microprocessors, Hardware