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11

ARC
2006
Springer

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Implementation of LPM Address Generators on FPGAs

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Implementation of LPM Address Generators on FPGAs

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Abstract. We propose the multiple LUT cascade as a means to configure an ninput LPM (Longest Prefix Match) address generator commonly used in routers to determine the output port given an address. The LPM address generator accepts n-bit addresses which it matches against k stored prefixes. We implement our

Hui Qin, Tsutomu Sasao, Jon T. Butler

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Address Generator | ARC 2006 | Hardware | LPM Address Generator | Multiple Lut Cascade |

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Added	20 Aug 2010
Updated	20 Aug 2010
Type	Conference
Year	2006
Where	ARC
Authors	Hui Qin, Tsutomu Sasao, Jon T. Butler

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