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FPL
2005
Springer

Mutable Codesign for Embedded Protocol Processing

10 years 3 months ago
Mutable Codesign for Embedded Protocol Processing
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs between the placement of protocol handling functions in programmable logic and on an embedded processor is demonstrated. This is facilitated by two new design tool capabilities: first, being able to describe programmable logic based functions in a more software-like manner; and second, being able automatically to generate efficient interfaces between a programmable logic fabric and an embedded processor. The methodology is illustrated by an example of a simple web server, targeted at Xilinx Virtex-II Pro or Virtex-4 FX platform FPGAs. Trade-offs both of complete protocol placement and of within-protocol placement are systematically investigated in terms of resources used and packet handling latency. This provides an excellent range of service times, corresponding to differing logic fabric and memory resour...
Todd S. Sproull, Gordon J. Brebner, Christopher E.
Added 27 Jun 2010
Updated 27 Jun 2010
Type Conference
Year 2005
Where FPL
Authors Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely
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