A dual-core 64b ultraSPARC microprocessor for dense server applications

A processor core, previously implemented in a 0.25m Al process, is redesigned for a 0.13m Cu process to create a dualcore processor with 1MB integrated L2 cache, offering an efficient performance/power ratio for compute-dense server applications. Deep submicron circuit design challenges, including negative bias temperature instability (NBTI), leakage and coupling noise, and L2 cache implementation are discussed. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Su, Ana Sonia Leon
• Keywords: Computer Architecture, DAC 2004, Design Styles, L2 Cache, Negative Bias Temperature Instability