High-Energy Physics on DECPeRLe-1 Programmable Active Memory

The future Large Hadron Collider (LHC) to be built at CERN1, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST2 (RD-11) group and DECPRL PAM3 team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1 [2]. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm [3]. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.

• Type: Conference
• Year: 1995
• Where: FPGA
• Authors: Laurent Moll, Jean Vuillemin, Philippe Boucard
• Keywords: Foremost Lhc Algorithms, FPGA, FPGA 1995, Large Hadron Collider, Real-time Computational Problems