A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment

Abstract-- Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause significant overhead in area and power consumption. To overcome the overhead, a fine-grained MCFPGA architecture using a floating-gate-MOS functional pass gate(FGFP) is presented which merges threshold operation and storage function on a single floating-gate MOS transistor. The test chip is designed using a 0.35

• Type: Conference
• Year: 2006
• Where: APCCAS
• Authors: Masanori Hariyama, Michitaka Kameyama
• Keywords: Additional Memory Planes, APCCAS 2006, Bit Forming Configuration, Hardware, Multiple Memory Bits