The Feasibility of Using Compression to Increase Memory System Performance

We investigate the feasibility of using instruction compression at some level in a multi-level memory hierarchy to increase memory system performance. Compression e ectively increases the memorysize and the line size reducing the miss rate at the expense of increased access latency due to decompression delays. We analyticallyevaluate the impact of compression on the average memory access time for various memory systems and compression approaches. Our results show the bene t of using compression is sensitive to the miss rates and miss penalties at the point of compression and to a lesser extent the amount of compression possible. For high performance workstations of today, compression already shows promise; as miss penalties increase in future, compression will only become more feasible.

• Type: Conference
• Year: 1994
• Where: MASCOTS
• Authors: Jenlong Wang, Russell W. Quong
• Keywords: Instruction Compression, MASCOTS 1994, MASCOTS 2007, Miss Penalties, Miss Rates