Conditional Memory Ordering

Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by executing a memory barrier instruction, ensuring that recent writes have been ordered with respect to other processors in the system. We show that this model leads to superfluous memory barriers in programs with acquire-release style synchronization, and present a combined hardware/software synchronization mechanism called conditional memory ordering (CMO) that reduces memory ordering overhead. CMO is demonstrated on a lock algorithm that identifies those dynamic lock/unlock operations for which memory ordering is unnecessary, and speculatively omits the associated memory ordering instructions. When ordering is required, this algorithm relies on a hardware mechanism for initiating a memory ordering operation on another processor. Based on evaluation using a software-only CMO prototype, we show that CMO avoids...

• Type: Journal
• Year: 2006
• Where: ISCA
• Authors: Christoph von Praun, Harold W. Cain, Jong-Deok Choi, Kyung Dong Ryu
• Keywords: Conventional Relaxed Memory, Hardware, ISCA 2006, Memory Barrier Instruction, Memory Barriers