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TC
2008

High-Performance Architecture of Elliptic Curve Scalar Multiplication

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High-Performance Architecture of Elliptic Curve Scalar Multiplication
A high performance architecture of elliptic curve scalar multiplication over finite field GF(2m ) is proposed. A pseudo-pipelined word serial finite field multiplier with word size w, suitable for the scalar multiplication is also developed. Implemented in hardware, this system performs a scalar multiplication in approximately 6m/w(m - 1) clock cycles and the gate delay in the critical path is equal to TAND + (log2 w)TXOR, where TAND and TXOR are delays due to two-input AND and XOR gates respectively.
B. Ansari, M. A. Hasan
Added 15 Dec 2010
Updated 15 Dec 2010
Type Journal
Year 2008
Where TC
Authors B. Ansari, M. A. Hasan
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