Multi-operand adder synthesis on FPGAs using generalized parallel counters

Multi-operand adders, which are also found in parallel multipliers, usually consist of the compression trees which reduce the number of operands per a bit to two, and the carrypropagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters like Wallace-trees in ASIC, though adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any larger or generalized parallel counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters with up to m inputs and synthesizes the compression trees to implement high-performance multi-operand adders by setting some intermediate height limits in the compression process like Dadda multipliers. Several experiments on Altera's Stratix III show its effectiveness against existing approaches.

• Type: Journal
• Year: 2010
• Where: ASPDAC
• Authors: Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
• Keywords: ASPDAC 2010, Compression Trees, Hardware, Multi-operand Adders, Parallel Counters