Energy and Delay Improvement via Decimal Floating Point Units

Interest in decimal arithmetic increased considerably in recent years. This paper presents new designs for decimal floating point (DFP) addition, multiplication, fused multiplyadd, division, and square root. It stresses the importance of energy savings achieved by hardware implementations of the IEEE standard for decimal floating point. To the best of the authors knowledge, this is the first work to discuss energy savings in DFP and the first to present a hardware implementation of a fused multiply-add. Our Newton-Raphson based divider is over three times faster than the similar design previously reported.

• Type: Conference
• Year: 2009
• Where: ARITH
• Authors: Hossam A. H. Fahmy, Ramy Raafat, Amira M. Abdel-Majeed, Rodina Samy, Tarek ElDeeb, Yasmin Farouk
• Keywords: Applied Computing, ARITH 2009, Decimal floating Point, Energy Savings, Hardware Implementation