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IFIP
2010
Springer
10 years 6 months ago
Combining Software and Hardware LCS for Lightweight On-Chip Learning
In this paper we present a novel two-stage method to realize a lightweight but very capable hardware implementation of a Learning Classifier System for on-chip learning. Learning C...
Andreas Bernauer, Johannes Zeppenfeld, Oliver Brin...
VLSID
2010
IEEE
190views VLSI» more  VLSID 2010»
10 years 9 months ago
A Reconfigurable Architecture for Secure Multimedia Delivery
This paper introduces a reconfigurable architecture for ensuring secure and real-time video delivery through a novel parameterized construction of the Discrete Wavelet Transform (D...
Amit Pande, Joseph Zambreno
CEE
2004
205views more  CEE 2004»
10 years 11 months ago
64-bit Block ciphers: hardware implementations and comparison analysis
A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are u...
Paris Kitsos, Nicolas Sklavos, Michalis D. Galanis...
VLSISP
2008
118views more  VLSISP 2008»
10 years 11 months ago
Analysis of Lifting and B-Spline DWT Implementations for Implantable Neuroprosthetics
Abstract. The large amount of data generated by neuroprosthetic devices requires a high communication bandwidth for extra-cranial transmission, critically limiting the number and u...
Awais M. Kamboh, Andrew Mason, Karim G. Oweiss
JUCS
2008
140views more  JUCS 2008»
10 years 12 months ago
Parallel Formulations of Scalar Multiplication on Koblitz Curves
We present an algorithm that by using the and -1 Frobenius operators concurrently allows us to obtain a parallelized version of the classical -and-add scalar multiplication algor...
Omran Ahmadi, Darrel Hankerson, Francisco Rodr&iac...
FCCM
2007
IEEE
168views VLSI» more  FCCM 2007»
11 years 3 days ago
Discrete-Time Cellular Neural Networks in FPGA
This paper describes a novel architecture for the hardware implementation of non-linear multi-layer cellular neural networks. This makes it feasible to design CNNs with millions o...
J. Javier Martínez-Álvarez, F. Javie...
CATA
2010
11 years 4 days ago
A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog
In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consum...
Bahram Hakhamaneshi, Behnam S. Arad
CHES
2010
Springer
187views Cryptology» more  CHES 2010»
11 years 1 months ago
Garbled Circuits for Leakage-Resilience: Hardware Implementation and Evaluation of One-Time Programs - (Full Version)
The power of side-channel leakage attacks on cryptographic implementations is evident. Today's practical defenses are typically attack-specific countermeasures against certain...
Kimmo Järvinen, Vladimir Kolesnikov, Ahmad-Re...
OSDI
1994
ACM
11 years 1 months ago
PathFinder: A Pattern-Based Packet Classifier
This paper describes a pattern-based approach to building packet classifiers. One novelty of the approach is that it can be implemented efficiently in both software and hardware. ...
Mary L. Bailey, Burra Gopal, Michael A. Pagels, La...
FPL
2008
Springer
137views Hardware» more  FPL 2008»
11 years 1 months ago
FPGA acceleration of Monte-Carlo based credit derivative pricing
In recent years the financial world has seen an increasing demand for faster risk simulations, driven by growth in client portfolios. Traditionally many financial models employ Mo...
Alexander Kaganov, Paul Chow, Asif Lakhany
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