Efficient statistical analysis of read timing failures in SRAM circuits

A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. Unlike existing approaches that focus on cell-level performance metrics for isolated sub-components or ignore inter-die variability, the system-level performance is accurately predicted for the entire SRAM circuit that is impractical to analyze statistically via transistor-level Monte Carlo simulations. The accurate bounding of read timing failures using this methodology is validated with silicon measurements from a 64kb SRAM testchip in 90nm CMOS. We demonstrate the efficacy of this methodology for earlystage design exploration to specify redundancy, required sense amp offset, and other circuit choices as a function of memory size. Keywords SRAM, failure analysis, response surface modeling

• Type: Conference
• Year: 2009
• Where: ISQED
• Authors: Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pileggi
• Keywords: Hardware, ISQED 2009, Read Timing Failures, SRAM Circuit, SRAM Circuit Blocks