A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management

An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while sustaining high frame rate. To this end, the proposed processor features from all levels of chip design. In architecture level, it performs 3-stage task pipelining for high frame rate operation and workload-aware dynamic power management for low power consumption. In block level, energy efficient special purposed engines are employed while software controlled clock gating is exploited for fine-grained clock control. In circuit level, analog-digital mixed design is used to reduce power with the same performance. As a result, the 49mm2 chip in a 0.13μm technology achieves 60fps object recognition for VGA

• Type: Conference
• Year: 2009
• Where: ISLPED
• Authors: Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim, Hoi-Jun Yoo
• Keywords: Energy Efficient, Hardware, ISLPED 2009, Object Recognition, Power Consumption