Coverage of a microarchitecture-level fault check regimen in a superscalar processor

Conventional processor fault tolerance based on time/space redundancy is robust but prohibitively expensive for commodity processors. This paper explores an unconventional approach to designing a cost-effective fault-tolerant superscalar processor. The idea is to engage a regimen of microarchitecture-level fault checks. A few simple microarchitecture-level fault checks can detect many arbitrary faults in large units, by observing microarchitecture-level behavior and anomalies in this behavior. Previously, we separately proposed checks for the fetch and decode stages, rename stage, and issue stage of a contemporary superscalar processor. While each piece hinted at the possibility of a complete regimen – for an overall faulttolerant superscalar processor – this totality was not explored. This paper provides the culmination by building a full regimen into a superscalar processor. We show for the first time that the regimen-based approach provides substantial coverage of an entire sup...

• Type: Conference
• Year: 2008
• Where: DSN
• Authors: Vimal K. Reddy, Eric Rotenberg
• Keywords: Computer Networks, DSN 2008, Fault-tolerant Superscalar Processor, Microarchitecture-level Fault Checks, Superscalar Processor