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ISCAS
2008
IEEE

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An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture

15 years 9 months ago

An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture

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Santanu Sarkar 0002, Ravi Sankar Prasad, Sanjoy Ku

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Added	31 May 2010
Updated	31 May 2010
Type	Conference
Year	2008
Where	ISCAS
Authors	Santanu Sarkar 0002, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee

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