A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme

We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is reduced by 25%, and the cell current is increased by 21%, compared with the prior 10T cell. The minimum operating voltage is lowered by the column line assist (CLA) scheme that suppresses write margin degradation. By measurement, we confirmed that the proposed 128-kb SRAM works at 0.56 V. Keywords SRAM, low-voltage operation

• Type: Conference
• Year: 2009
• Where: ISQED
• Authors: Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
• Keywords: Cell, Hardware, ISQED 2009, Prior 10T Cell, SRAM Cell