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JCP
2008
141views more  JCP 2008»
9 years 11 months ago
Leakage Controlled Read Stable Static Random Access Memories
Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a criti...
Sayeed A. Badrudduza, Ziyan Wang, Giby Samson, Law...
ISLPED
1996
ACM
103views Hardware» more  ISLPED 1996»
10 years 3 months ago
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving
This paper proposes a 0.5V / 100MHz / sub-5mW-operated 1-Mbit SRAM cell architecture which uses an overVCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimi...
Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, ...
ISLPED
2005
ACM
119views Hardware» more  ISLPED 2005»
10 years 5 months ago
FinFET-based SRAM design
Intrinsic variations and challenging leakage control in today’s bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRA...
Zheng Guo, Sriram Balasubramanian, Radu Zlatanovic...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
10 years 5 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
ISQED
2006
IEEE
259views Hardware» more  ISQED 2006»
10 years 5 months ago
Impact of NBTI on SRAM Read Stability and Design for Reliability
— Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious ...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
ISCAS
2007
IEEE
132views Hardware» more  ISCAS 2007»
10 years 5 months ago
High Read Stability and Low Leakage Cache Memory Cell
- Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines...
Zhiyu Liu, Volkan Kursun
SOCC
2008
IEEE
121views Education» more  SOCC 2008»
10 years 6 months ago
Low power 8T SRAM using 32nm independent gate FinFET technology
In this paper, new SRAM cell design methods for FinFET technology are proposed. One of the most important features of FinFET is that the independent front and back gate can be bia...
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
GLVLSI
2008
IEEE
190views VLSI» more  GLVLSI 2008»
10 years 6 months ago
A low leakage 9t sram cell for ultra-low power operation
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
ISQED
2009
IEEE
196views Hardware» more  ISQED 2009»
10 years 6 months ago
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is redu...
Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto...
ISQED
2010
IEEE
135views Hardware» more  ISQED 2010»
10 years 6 months ago
Signal probability control for relieving NBTI in SRAM cells
—Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage degradation in a PMOS transistor wh...
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
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