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1996
ACM

A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving

12 years 1 months ago
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving
This paper proposes a 0.5V / 100MHz / sub-5mW-operated 1-Mbit SRAM cell architecture which uses an overVCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimize the charge amount supplied from the embedded charge pump circuits, which are required to boost the effective gate to source voltage (VO=VGS-VT) up to 0.8V necessary to achieve 100MHz-operation even at 0.5V single power-supply. Thus, the key low-power strategy of OVGS is "putting the right (higher efficiency) boosted power-supply from charge pump circuit into the right position (less power consumed transistor) in a SRAM cell". This paper is focused on why OVGS can realize a greater savings of the charge amount supplied from the boosted power-line and can reduce the power dissipation to 1/30.4 and 1/3.9 compared to the previously reported negative source drive (NSD) scheme[1] and negative word-line drive (NWD) scheme[2], respectively, while achieving a 0.5V / 100MHzoperation.
Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu,
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1996
Where ISLPED
Authors Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa
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